(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to create a self-aligned contact opening, for a capacitor structure.
(2) Description of Prior Art
The advent of the self-aligned contact, (SAC), opening, has contributed to the objective of increasing the density of semiconductor chips. The SAC opening, as used with metal oxide semiconductor field effect transistors, (MOSFET), allows the entire width of a source/drain region, located between gate structures, to be exposed, and to be subsequently contacted by an overlying conductive structure. The SAC opening comprises the exposure of the entire source/drain region, located in the space between gate structures, as well as the exposure of a portion of insulator capped, gate structures. Thus the SAC opening eliminates the need to form a fully landed contact hole to the source/drain region, and thus allows the space between the gate structures, to be less than the minimum photolithographic feature used, resulting in increased device density. The use of a SAC opening is made possible via use a reactive ion etching, (RIE), procedure, featuring a high etch rate ratio, or selectivity, between a silicon oxide layer, located between, as well as overlying, the insulator capped, gate structures, and the silicon nitride, or silicon oxynitride layer, used for the hard mask, or capping layer. However difficulties can be encountered earlier, when depositing the silicon oxide layer, in the high aspect ratio space between the insulator capped, gate structures. Undesirable seams or voids, can form at the point where the silicon oxide layers, on the sides of the insulator capped, gate structures, converge. The subsequent SAC opening will expose the seam or void, at the perimeter of the SAC opening, presenting a possible leakage or shorting mechanism, between the conductive structure formed in the SAC opening, and adjacent conductive structures.
This invention will provide a process in which the seam or void, in the silicon oxide layer, is repaired by forming a silicon nitride liner on the exposed sides of the silicon oxide layer, at the perimeter of the SAC opening. In addition this invention will provide a process used to recess back a top portion of the silicon nitride liner, however still leaving a bottom portion of the silicon nitride liner to protect the voids or seams in the portion of the silicon oxide layer located between the gate structures. This in turn allows a top portion of the silicon oxide layer to be recessed via a selective wet etch procedure, after the formation of a polysilicon storage node structure on the inside walls of the SAC opening, resulting in the additional exposure of polysilicon storage node surface, and thus increased capacitance for a crown shaped capacitor structure, located in the SAC opening. Prior art, such as Yang et al, in U.S. Pat. No. 5,792,689, as well as Chen, in U.S. Pat. No. 5,736,441, describe crown shaped capacitors, in SAC openings, however neither prior art describe the process for forming a silicon nitride liner, on the sides of the SAC opening, located between gate structures.